A radiation-hardened optical receiver chip

A novel radiation hardened by design latch ∗

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the pr...

RAD750 Radiation Hardened PowerPC Microprocessor

The development of a high performance radiation hardened PowerPC microprocessor is nearing completion. The features of the RAD750 are described, as well as the process of radiation hardening the processor. The RAD750 product family includes a PCI support chip and a CompactPCI 3U board, both of which are described.

A 25Gb/s 170μW/Gb/s Optical Receiver in 28nm CMOS for Chip-to-Chip Optical Communication

A low-power high-speed optical receiver in 28nm CMOS is presented. The design features a novel architecture combining a low-bandwidth TIA front-end, double-sampling technique and dynamic offset modulation. The low-bandwidth TIA increases receiver’s sensitivity while adding minimal power overhead. Functionality of the receiver was validated and the design is compared with a conventional 3-stage ...

Linear Mode Operation of Radiation Hardened MOSFETS

Expecting the Unexpected - Radiation Hardened Software

Radiation induced Single Event Effects (SEEs) are a serious problem for spacecraft flight software, potentially leading to a complete loss of mission. Conventional risk mitigation has been focused on hardware, leading to slow, expensive and outdated on-board computing devices, increased power consumption and launch mass. Our approach is to look at SEEs from a software perspective, and to explic...